FIG. 1 is a cross-sectional view of a portion of a prior art insulated gate turn-off (IGTO) device 10 described in U.S. Pat. No. 7,705,368, incorporated herein by reference. An NPNP semiconductor layered structure is formed. In FIG. 1, there is a PNP transistor formed by a p+ substrate 12, an n-type layer 14, and a p-well 16. There is also an NPN transistor formed by the layer 14, the p-well 16, and an n+ layer 18. A bottom anode electrode 20 contacts the substrate 12, and a top cathode electrode 22 contacts the n+ layer 18. Trenches 24, coated with an oxide layer 25, contain a conductive gate material 26 (forming interconnected vertical gate regions) which is contacted by a gate electrode 28. The p-well 16 surrounds the gate structure, and the n-type layer 14 extends to the surface around the p-well 16. Outside of the cross-section, the cathode electrode 22 may contact the p-well 16.
When the anode electrode 20 is forward biased with respect to the cathode electrode 22, but without a sufficiently positive gate bias, there is no current flow, since the product of the betas (gains) of the PNP and NPN transistors is less than one.
When there is a sufficient positive voltage (e.g., 2 volts) applied to the gate, and there is a sufficient forward-biasing anode-cathode voltage, electrons from the n+ layer 18 become the majority carriers along the sidewalls and below the bottom of the trenches 24 in an inversion layer, causing the effective width of the NPN base (the portion of the p-well 16 below the trenches 24) to be reduced. As a result, the beta of the NPN transistor increases to cause the product of the betas to exceed one. This results in “breakover,” when holes are injected into the lightly doped n-type layer 14 and electrons are injected into the p-well 16 to fully turn on the device. This is a controlled latch-up of the device. Accordingly, the gate bias initiates the turn-on, and the full turn-on is accomplished by the current flow through the NPN and PNP transistors.
According to the '368 patent, when the gate bias is made negative (e.g., −2 volts), the IGTO device turns off.
Such IGTO devices have a relatively high current density when on. In contrast, insulated gate bipolar transistors (IGBTs) generally have a lower current density when on. Accordingly, for at least high current applications, IGTO devices are preferred. Further, IGTO devices are typically used as on-off switches, while IGBTs may be used to smoothly modulate current.
The processing steps for forming trenched gates are time-consuming and therefore expensive. Further, the depth of the trench affects the turn-on voltage, and there is typically an undesired variation in gate trench depth from lot to lot. It follows that the gate voltage needed to decrease the NPN transistor base width to cause the product of the gains to exceed one (to initiate turn-on) is difficult to reproduce from one lot of IGTO devices to another.
Therefore, what is needed is a new design for an IGTO device that does not require a trenched gate and does not have the above-mentioned drawbacks.